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Careers

Position:

Memory Qualification Manager

Location:

  • Switzerland or Israel

Role Description:

  • Leading the full-custom embedded memory IP qualification process.
  • Supervision and interpretation of silicon testing results.
  • Definition of reliability & test requirements, qualification and test procedures, and design-for-test (DFT) IPs.
  • Characterization and modelling of memory IPs.
  • Memory Compiler verification and Quality Control (QC).
  • Frequent interaction with foundries.

Requirements:

  • Experience in leading IP qualification flows, preferably memory IPs.
  • Extensive memory design and memory compiler experience.
  • Experience with advanced technology nodes is preferable.
  • Ideally at least 10 years of industry experience.
  • Must have good team work and be able to work under pressure.

Position:

Full-Custom Design Engineer

Location:

  • Switzerland or Israel

Role Description:

  • Design and implementation of custom analog/digital circuits for integration in state-of-the-art embedded memories.
  • Define architectures/topologies to optimize power, timing, area, and yield.
  • Characterization and modeling of memory IPs.

Requirements:

  • Transistor-level VLSI circuit design.
  • Experience with Cadence EDA (Virtuoso/Composer/ Layout).
  • Hands-on experience in circuit designs for memory or analog blocks (SRAM, DRAM, etc.,).
  • Experience with advanced process nodes (28nm and below).

Position:

SoC Design Engineer​

Location:

  • Switzerland or Israel

Role Description:

  • Front-End + Back-End (RTL2GDS) design of memory test-chips in advanced technology nodes.
  • Definition of chip architecture and implementation (RTL, verification, backend).
  • Developing a verification environment for block level and full chip.

Requirements:

  • Experience in chip-design and tapeout.
  • Knowledge in RTL2GDS tools and flows.
  • BSc in Electrical Engineering, MSc is an advantage.
  • Experience with advanced process nodes (28nm and below).

Position:

Research Engineer (possibility for PhD route in TCL-EPFL)

Location:

  • Switzerland or Israel

Role Description:

  • Research of advanced circuit design techniques to optimize memory circuits and peripherals.

Requirements:

  • MSc in electrical engineering.
  • Experience in transistor-level VLSI circuit design.
  • Experience with Cadence EDA (Virtuoso/Composer
    /Layout).

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