RAAAM™ Technologies provides the highest-density embedded memory in any standard CMOS technology

Careers

Position:

Physical Design Engineer

Job description

Physical Design Engineer responsible for the implementation and signoff of RAAAM’s next-generation embedded memories test chips across a variety of advanced CMOS technologies.

Responsibilities

  • Execute various Place and Route (P&R) tasks from RTL to GDSII.
  • Perform comprehensive design signoff, including STA, EMIR, DRC, and LVS.
  • Work extensively with a variety of process nodes, focusing on advanced technologies down to 2nm and beyond.
  • Automate design and physical verification flows to improve efficiency.
  • Collaborate closely with circuit design and integration teams.

Qualifications

  • 2+ years of experience in Physical Design (RTL to GDS).
  • Hands-on experience with Cadence EDA tools, specifically Genus and Innovus.
  • Strong understanding of physical design signoff processes (STA, DRC, LVS).
  • Independent in his work and strives to bring results
  • High proficiency in scripting, automation, and Linux environments (e.g., TCL, Python, Bash).
  • MSc./ BSc. degree in Electrical / Computer Engineering.

Location

  • Israel or Switzerland

Full / Part Time

  • Full time

Position:

Device Engineer

Job description

We are looking for a highly motivated, Technology / Device / Process Engineer to lead the development of our next-generation GCRAM technology. In this role, you will pioneer the device and process engineering required to bring our next-generation memory architecture to life. You will work closely with top-tier scientific advisors and collaborate with leading external research and development partners to drive device and process development, device fabrication, characterization, and process integration and interface with circuit engineers. This is an ideal role for a recent PhD graduate looking to transition cutting-edge academic research into industry-disrupting commercial hardware.

Responsibilities

  • Lead the process development, fabrication path, and electrical characterization and modelling for our next-generation GCRAM technology.
  • Collaborate with external R&D partners to define, optimize, and run integration flows for next-generation GCRAM devices.
  • Act as the primary technical interface between RAAAM and R&D partners to align fabrication runs with simulation and design models.
  • Oversee electrical measurements (I-V, C-V, reliability, and stability testing) on fabricated test structures and develop models to guide our circuit design team.
  • Evaluate and benchmark different process recipes, device architectures and structures, and materials to optimize next-generation GCRAM performance.

Qualifications

  • PhD degree in Electrical Engineering, Materials Science, Physics, or a closely related field, with a research focus on advanced semiconductor devices, novel device architectures, or advanced process integration.
  • Strong background in semiconductor device physics and extensive experience with TCAD simulation tools (e.g., Synopsys Sentaurus, Silvaco)
  • Collaboration & Communication: Excellent communication skills and the ability to work independently in a highly collaborative, multi-partner environment (academic advisors, external research organizations, and internal circuit design teams).
  • Preferred / Advantage: Hands-on experience with advanced semiconductor device fabrication, characterization, or process integration and prior cleanroom fabrication experience.
  • Advantage: basic background in microelectronics and circuit design.

Location

  • Lausanne, Switzerland

Full / Part Time

  • Full time

Position:

VLSI Circuit Design

Job description

Analog / Digital transistor-level circuit verification of RAAAM’s next generation embedded memories
in advanced CMOS technologies.

Responsibilities

  • Design of RAAAM’s embedded memories in advanced CMOS technologies.
  • Analysis and optimization of read and write critical paths.
  • Top-level Analog verification and characterization of all circuit components.
  • Automation of design verification flows.
  • Generation of back-end views for chip integration.

Qualifications

  • 5+ years of experience with full-custom circuit design (Schematics, Layout, Verification).
  • Experience in advanced process node circuit design (16nm and below).
  • Experience with Cadence EDA environment (Virtuoso/Composer/Layout).
  • High proficiency in scripting, automation, and Linux environments.
  • Good knowledge and experience with Python coding.
  • BSc. degree in Electrical / Computer Engineering.

Location

  • Israel or Switzerland

Full / Part Time

  • Full time

Send resume to email: [email protected]